Computations performed on real numbers in science and engineering typically require numbers whose magnitudes may vary greatly. The typical prior art solution for representing such numbers is to use a floating point number system, such as the IEEE 754 standard. One disadvantage of prior art floating point processors is that they require expensive circuits with high power consumption to achieve high speed operation. Another disadvantage of floating point is that all four basic arithmetic operations (addition, subtraction, multiplication, and division) can produce roundoff errors, as described by Barlow and Bareiss in "On Roundoff Distributions in Floating Point and Logarithmic Arithmetic", Computing, vol. 34, pp. 325-347, 1985. To overcome the speed, cost and accuracy disadvantages of floating point, the use of logarithmic number systems for limited precision computers has been suggested in the prior art, as typified by U.S. Pat. No. 4,531,124. Multiplication and division of numbers represented in logarithmic form is inexpensive and accurate, since the logarithm of a product is the sum of the logarithms of the numbers being multiplied, and the logarithm of a quotient is the difference of the logarithms of the numbers being divided.
The more challenging aspect of logarithmic arithmetic is the computation of the sum and differences of the numbers being represented as logarithms. First implemented by Kingsbury and Rayner, "Digital Filtering Using Logarithmic Arithmetic", Electronics Letters, Vol 7, pp. 56-58, 1971, addition and subtraction can be implemented by adding a correction term to the smaller of the two logarithms. Since ##EQU1## addition in the sign logarithm number system requires three hardware units: a fixed point subtractor that produces the difference of the logarithms, an approximation unit that computes s.sub.b, and a fixed point adder. Also ##EQU2## and so, provided that the approximation unit can be selected to produce either s.sub.b or d.sub.b, the same hardware can be used for both addition or subtraction. By including a sign bit with every word, the sign logarithm number system makes it possible for simple logic to select whether s.sub.b or d.sub.b need be computed. (Such logic is similar to that used for addition and subtraction of signed magnitude numbers.)
The central aspect of logarithmetic arithmetic is the computation of s.sub.b and d.sub.b. When the application only demands limited precision, tabular methods, typically implemented with ROMs or PLAs, can be used to approximate s.sub.b and d.sub.b. For example, see Lang et al, "Integrated Circuit Logarithmic Arithmetic Units", IEEE Transactions on Computers, Vol C-34, pp 475-483, 1985. However, if the application requires a word size of more than 8 to 16 bits, simple ROM or PLA implementations are not suitable because the circuit complexity grows exponentially as the number of bits in the word increases. A floating point word size of 32 bits is regarded as the smallest acceptable size for real arithmetic on a general purpose computer, where the nature of the computation is not known when the hardware is designed. The prior art ROM and PLA implementations of s.sub.b and d.sub.b are not suitable for a general purpose computer.
To overcome the restrictions of the prior art, linear interpolation of s.sub.b has been suggested in Arnold, "Extending the Precision of the Sign Logarithm Number System," M. S. Thesis, University of Wyoming, 1982. Using current technology, such interpolation provides sufficient accuracy for 32 bit logarithmic addition. However, the apparatus described therein is not suitable for approximating d.sub.b (z), because as z approaches zero the errors introduced by linear approximation increase. Other than the expensive and slow process of separately computing the logarithm and antilogarithm in log.sub.b .vertline.1-b.sup.z .vertline. by methods typified by U.S. Pat. Nos. 4,583,180, 3,631,230 and 3,402,285, there is no practical, high speed, prior art method for approximating d.sub.b that is accurate enough for 32 bit logarithmic subtraction.
Accordingly, it is an object of the present invention to compute differences of numbers represented in logarithmic form with accuracy suitable for general purpose computation.
Another object of the present invention is to reduce the memory required to achieve the desired precision.
Yet another object of the present invention is to allow computation of log.sub.b (1+b.sup.z) by selectively bypassing portions of the hardware used for computing log.sub.b .vertline.1-b.sup.z .vertline..
Still another object of the present invention is to allow computation of log.sub.b .vertline.1-b.sup.z .vertline. for values of z near zero with the required accuracy for 32 bit operation by transforming the problem into one of computing log.sub.b (1+b.sup.z).